Result Details:

Overall Summary + details of 5 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig	Test Frequency(MHz)	Total Jitter with Zoomed Out Screen	Std Dev(ps)	Tbit(ps)	Clock Jitter(ps)	# Samples	# Edges	Acquisition Bandwidth (GHz)
	Avg	65.59 mTbit	73.76 %
	StdDev	53.89 mTbit	21.61 %
	Range	130.4 mTbit	52.40 %
	Min	8.157 mTbit	44.40 %
	Max	138.5 mTbit	96.80 %
	Sum	327.9 mTbit	368.8 %
	Trial 1 (Worst)	139 mTbit	44.4%	Timing 95	297.001	(See image)	5.473	336.699	46.640	16.000000000 M	0.000	13.000
	Trial 2	99 mTbit	60.4%	Timing 16_36_444	222.750	(See image)	5.096	448.934	44.650	16.000000000 M	0.000	13.000
	Trial 3	59 mTbit	76.4%	Timing 16	148.500	(See image)	5.133	673.400	39.540	16.000000000 M	0.000	13.000
	Trial 4	23 mTbit	90.8%	Timing 4	74.250	(See image)	4.431	1.346801 k	31.090	16.000000000 M	0.000	13.000
	Trial 5	8 mTbit	96.8%	Timing 2	27.000	(See image)	4.278	3.703700 k	30.210	16.000000000 M	0.000	13.000

Trial 1

Trial 1: Total Jitter with Zoomed Out Screen

Trial 1: Clock Jitter

Trial 2

Trial 2: Total Jitter with Zoomed Out Screen

Trial 2: Clock Jitter

Trial 3

Trial 3: Total Jitter with Zoomed Out Screen

Trial 3: Clock Jitter

Trial 4

Trial 4: Total Jitter with Zoomed Out Screen

Trial 4: Clock Jitter

Trial 5

Trial 5: Total Jitter with Zoomed Out Screen

Trial 5: Clock Jitter

7-4: Clock Rise Time Reference: Test ID 7-4

Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>= 75.000 psRaw Clock Transition Time175.175 ps

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Upper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)336 mVBase(V)-336 mUpper Threshold(V)202 mLower Threshold(V)-202 m# Edges118.799000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum) Reference: Test ID 7-8

Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>=40%Clock Duty Cycle Minimum50.170

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001# Edges10.000000 kTdutyMIN(ns)1.689

Trial 1

Trial 1: Clock Duty Cycle Minimum

7-8: Clock Duty Cycle(Maximum) Reference: Test ID 7-8

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001# Edges10.000000 kTdutyMAX(ns)1.711

Trial 1

Trial 1: Clock Duty Cycle Maximum

7-2: VL Clock + Reference: Test ID 7-2

Test Summary: Pass Test Description: The Source shall meet the DC specifications in Table 4-12 for all operating conditions specified in Table 4-11 when driving clock and data signals. For compliance, the DUT should output the lowest supported pixel clock frequency during the test.
Pass Limits:[LowerLimit V to 2.900 V]VL (Worst of 2 Trials)2.847 V # Trials Run: 2Worst Trial: Trial 1

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges	DUT supports clock rates > 165MHz
	Avg	2.849 V	21.33 %	3.299 V	2.650 V
	StdDev	1.697 mV	5.185 %	141.4 µV	70.71 mV
	Range	2.400 mV	7.333 %	200.0 µV	100.0 mV
	Min	2.847 V	17.67 %	3.299 V	2.600 V
	Max	2.850 V	25.00 %	3.299 V	2.700 V
	Sum	5.697 V	42.67 %	6.597 V	5.300 V
	Trial 1 (Worst)	2.847 V	17.7%	3.299 V	2.600 V	Timing 2	27.000 MHz	10.762000 k	true
	Trial 2	2.850 V	25.0%	3.299 V	2.700 V	Timing 2	27.000 MHz	10.762000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL Clock - Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges	DUT supports clock rates > 165MHz
	Avg	2.860 V	16.58 %	3.300 V	2.650 V
	StdDev	997.0 µV	4.125 %	205.1 µV	70.71 mV
	Range	1.410 mV	5.833 %	290.0 µV	100.0 mV
	Min	2.859 V	13.67 %	3.300 V	2.600 V
	Max	2.861 V	19.50 %	3.300 V	2.700 V
	Sum	5.720 V	33.17 %	6.599 V	5.300 V
	Trial 1 (Worst)	2.859 V	13.7%	3.300 V	2.600 V	Timing 2	27.000 MHz	10.763000 k	true
	Trial 2	2.861 V	19.5%	3.300 V	2.700 V	Timing 2	27.000 MHz	10.763000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Clock Reference: Test ID 7-7

Test Summary: Pass Test Description: Frequency > 165 MHz: Intra-Pair Skew must not exceed 0.15*Tbit. The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:[-150 mTbit to 150 mTbit]Clock Intra-Pair Skew9 mTbit

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)16.170Min skew (ps)-11.250Mean skew (ps)2.958Std Dev (ps)3.511Clk+ threshold (V)3.107Clk- threshold (V)3.091Acquisition Bandwidth (GHz)13.000NumEdges17.602000 kTest Frequency(MHz)297.000Clock Intra-Pair Skew(ps)3.050Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D0 Mask Test Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:No Mask FailuresTotal # failures (Worst of 5 Trials)0.000 # Trials Run: 5Worst Trial: Trial 1

Result Details:

Overall Summary + details of 5 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

250.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

298.359

642.000

297.001

10.960

16.000000000 M

336.699

115 m

113 m

38.734

38.211

384 m

-351 m

735 m

13.000

Trial 2

0.000

50.0%

Timing 16_36_444

405.703

559.000

222.750

22.910

16.000000000 M

448.934

97 m

96 m

43.594

42.891

382 m

-347 m

729 m

13.000

Trial 3

0.000

50.0%

Timing 16

634.470

506.000

148.500

0.000

16.000000000 M

673.396

59 m

56 m

39.980

37.880

338 m

-305 m

643 m

13.000

Trial 4

0.000

50.0%

Timing 4

1.313130 k

570.000

74.250

0.000

16.000000000 M

1.346807 k

27 m

25 m

35.770

33.670

359 m

-322 m

682 m

13.000

Trial 5

0.000

50.0%

Timing 2

3.674770 k

600.000

27.000

0.000

16.000000000 M

3.703700 k

8 m

28.940

361 m

-323 m

684 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

Trial 5

Trial 5: Total # failures

7-10: D0 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 5 Trials)115 m # Trials Run: 5Worst Trial: Trial 1

Result Details:

Overall Summary + details of 5 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	61.18 m	79.60 %
	StdDev	45.39 m	15.07 %
	Range	107.2 m	35.67 %
	Min	7.814 m	61.67 %
	Max	115.0 m	97.33 %
	Sum	305.9 m	398.0 %
	Trial 1 (Worst)	115 m	61.7%	Timing 95
	Trial 2	97 m	67.7%	Timing 16_36_444
	Trial 3	59 m	80.3%	Timing 16
	Trial 4	27 m	91.0%	Timing 4
	Trial 5	8 m	97.3%	Timing 2

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

Trial 5

Trial 5: TbitCheck

7-4: D0 Rise Time Reference: Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>= 75.000 psTransition Time81.951 ps

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Data Lane AD0Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)384 mVBase(V)-351 mUpper Threshold(V)237 mLower Threshold(V)-204 m#Edge228.905000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D0 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D0+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.794 V	41.42 %	3.135 V	2.650 V
	StdDev	416.5 µV	8.603 %	628.6 µV	70.71 mV
	Range	589.0 µV	12.17 %	889.0 µV	100.0 mV
	Min	2.794 V	35.33 %	3.135 V	2.600 V
	Max	2.795 V	47.50 %	3.136 V	2.700 V
	Sum	5.589 V	82.83 %	6.271 V	5.300 V
	Trial 1 (Worst)	2.794 V	35.3%	3.135 V	2.600 V	Timing 2	27.000 MHz	9.082000 k	9.854000 k	true
	Trial 2	2.795 V	47.5%	3.136 V	2.700 V	Timing 2	27.000 MHz	9.093000 k	9.831000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D0- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.799 V	41.58 %	3.132 V	2.650 V
	StdDev	333.0 µV	11.20 %	515.5 µV	70.71 mV
	Range	471.0 µV	15.83 %	729.0 µV	100.0 mV
	Min	2.799 V	33.67 %	3.132 V	2.600 V
	Max	2.799 V	49.50 %	3.132 V	2.700 V
	Sum	5.598 V	83.17 %	6.264 V	5.300 V
	Trial 1 (Worst)	2.799 V	33.7%	3.132 V	2.600 V	Timing 2	27.000 MHz	9.948000 k	10.187000 k	true
	Trial 2	2.799 V	49.5%	3.132 V	2.700 V	Timing 2	27.000 MHz	9.696000 k	10.077000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 0 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)16.660Min skew (ps)-1.690Mean skew (ps)6.832Std Dev (ps)2.241D+ threshold (V)2.783D- threshold (V)2.750Acquisition Bandwidth (GHz)13.000NumEdges16.354000 kTest Frequency(MHz)299.218Data Intra-Pair Skew(ps)6.330Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D1 Mask Test Reference: Test ID 7-10

Result Details:

Overall Summary + details of 5 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

250.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

300.453

636.000

297.001

12.180

16.000000000 M

336.698

107 m

36.117

350 m

-394 m

744 m

13.000

Trial 2

0.000

50.0%

Timing 16_36_444

403.340

573.000

222.750

0.000

16.000000000 M

448.935

102 m

45.590

341 m

-375 m

716 m

13.000

Trial 3

0.000

50.0%

Timing 16

635.520

501.000

148.500

0.000

16.000000000 M

673.405

56 m

37.880

319 m

-352 m

670 m

13.000

Trial 4

0.000

50.0%

Timing 4

1.313130 k

579.000

74.250

0.000

16.000000000 M

1.346809 k

27 m

25 m

35.770

33.670

321 m

-352 m

672 m

13.000

Trial 5

0.000

50.0%

Timing 2

3.674770 k

496.000

27.000

0.000

16.000000000 M

3.703690 k

8 m

28.940

263 m

-296 m

559 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

Trial 5

Trial 5: Total # failures

7-10: D1 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 5 Trials)107 m # Trials Run: 5Worst Trial: Trial 1

Result Details:

Overall Summary + details of 5 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	59.89 m	80.00 %
	StdDev	44.21 m	14.70 %
	Range	99.45 m	33.00 %
	Min	7.814 m	64.33 %
	Max	107.3 m	97.33 %
	Sum	299.4 m	400.0 %
	Trial 1 (Worst)	107 m	64.3%	Timing 95
	Trial 2	102 m	66.0%	Timing 16_36_444
	Trial 3	56 m	81.3%	Timing 16
	Trial 4	27 m	91.0%	Timing 4
	Trial 5	8 m	97.3%	Timing 2

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

Trial 5

Trial 5: TbitCheck

7-4: D1 Rise Time Reference: Test ID 7-4

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Data Lane AD1Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)350 mVBase(V)-394 mUpper Threshold(V)201 mLower Threshold(V)-245 m#Edge270.739000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D1 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D1+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.878 V	8.917 %	3.162 V	2.650 V
	StdDev	854.2 µV	2.239 %	560.0 µV	70.71 mV
	Range	1.208 mV	3.167 %	792.0 µV	100.0 mV
	Min	2.878 V	7.333 %	3.162 V	2.600 V
	Max	2.879 V	10.50 %	3.163 V	2.700 V
	Sum	5.757 V	17.83 %	6.325 V	5.300 V
	Trial 1 (Worst)	2.878 V	7.3%	3.163 V	2.600 V	Timing 2	26.975 MHz	38.000	646.000	true
	Trial 2	2.879 V	10.5%	3.162 V	2.700 V	Timing 2	26.974 MHz	9.143000 k	9.692000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D1- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.882 V	7.667 %	3.159 V	2.650 V
	StdDev	712.1 µV	1.886 %	1.268 mV	70.71 mV
	Range	1.007 mV	2.667 %	1.793 mV	100.0 mV
	Min	2.881 V	6.333 %	3.159 V	2.600 V
	Max	2.882 V	9.000 %	3.160 V	2.700 V
	Sum	5.764 V	15.33 %	6.319 V	5.300 V
	Trial 1 (Worst)	2.881 V	6.3%	3.160 V	2.600 V	Timing 2	26.975 MHz	9.639000 k	9.066000 k	true
	Trial 2	2.882 V	9.0%	3.159 V	2.700 V	Timing 2	26.974 MHz	714.000	63.000	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 1 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)16.450Min skew (ps)-2.950Mean skew (ps)6.480Std Dev (ps)2.603D+ threshold (V)2.784D- threshold (V)2.753Acquisition Bandwidth (GHz)13.000NumEdges16.366000 kTest Frequency(MHz)294.924Data Intra-Pair Skew(ps)5.910Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D2 Mask Test Reference: Test ID 7-10

Result Details:

Overall Summary + details of 5 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

250.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

297.760

594.000

297.001

0.000

16.000000000 M

336.699

116 m

38.930

332 m

-360 m

692 m

13.000

Trial 2

0.000

50.0%

Timing 16_36_444

404.297

500.000

222.750

32.730

16.000000000 M

448.938

100 m

99 m

45.000

44.297

303 m

-328 m

631 m

13.000

Trial 3

0.000

50.0%

Timing 16

633.867

508.000

148.500

22.090

16.000000000 M

673.405

60 m

58 m

40.078

39.023

330 m

-356 m

686 m

13.000

Trial 4

0.000

50.0%

Timing 4

1.308920 k

505.000

74.250

0.000

16.000000000 M

1.346795 k

28 m

37.880

286 m

-312 m

597 m

13.000

Trial 5

0.000

50.0%

Timing 2

3.674770 k

615.000

27.000

0.000

16.000000000 M

3.703711 k

8 m

28.940

335 m

-362 m

698 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

Trial 5

Trial 5: Total # failures

7-10: D2 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 5 Trials)116 m # Trials Run: 5Worst Trial: Trial 1

Result Details:

Overall Summary + details of 5 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	62.29 m	79.20 %
	StdDev	45.96 m	15.31 %
	Range	108.2 m	36.03 %
	Min	7.814 m	61.30 %
	Max	116.0 m	97.33 %
	Sum	311.5 m	396.0 %
	Trial 1 (Worst)	116 m	61.3%	Timing 95
	Trial 2	100 m	66.7%	Timing 16_36_444
	Trial 3	60 m	80.0%	Timing 16
	Trial 4	28 m	90.7%	Timing 4
	Trial 5	8 m	97.3%	Timing 2

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

Trial 5

Trial 5: TbitCheck

7-4: D2 Rise Time Reference: Test ID 7-4

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.997Data Lane AD2Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)331 mVBase(V)-358 mUpper Threshold(V)193 mLower Threshold(V)-220 m#Edge258.517000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D2 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D2+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.779 V	40.17 %	3.131 V	2.650 V
	StdDev	627.9 µV	235.7 m%	149.9 µV	70.71 mV
	Range	888.0 µV	333.3 m%	212.0 µV	100.0 mV
	Min	2.779 V	40.00 %	3.131 V	2.600 V
	Max	2.780 V	40.33 %	3.131 V	2.700 V
	Sum	5.558 V	80.33 %	6.262 V	5.300 V
	Trial 1	2.779 V	40.3%	3.131 V	2.600 V	Timing 2	26.977 MHz	7.862000 k	8.298000 k	true
	Trial 2 (Worst)	2.780 V	40.0%	3.131 V	2.700 V	Timing 2	26.968 MHz	6.809000 k	8.127000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D2- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.784 V	40.08 %	3.127 V	2.650 V
	StdDev	140.7 µV	2.003 %	212.8 µV	70.71 mV
	Range	199.0 µV	2.833 %	301.0 µV	100.0 mV
	Min	2.783 V	38.67 %	3.127 V	2.600 V
	Max	2.784 V	41.50 %	3.127 V	2.700 V
	Sum	5.567 V	80.17 %	6.254 V	5.300 V
	Trial 1 (Worst)	2.784 V	38.7%	3.127 V	2.600 V	Timing 2	26.977 MHz	2.018000 k	1.582000 k	true
	Trial 2	2.783 V	41.5%	3.127 V	2.700 V	Timing 2	26.968 MHz	6.922000 k	7.413000 k	false

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 2 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)7.170Min skew (ps)-13.290Mean skew (ps)-5.807Std Dev (ps)2.351D+ threshold (V)2.803D- threshold (V)2.770Acquisition Bandwidth (GHz)13.000NumEdges15.985000 kTest Frequency(MHz)297.000Data Intra-Pair Skew(ps)-5.700Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-6: Inter-Pair Skew - D0/D1 Reference: Test ID 7-6

Test Summary: Pass Test Description: Inter-pair skew must not exceed 0.20*Tpixel. The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:[-200 mTpixel to 200 mTpixel]Data - Data Inter-Pair Skew2 mTpixel

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Data Lane AD0Data Lane BD1Data - Data Inter-Pair Skew(ps)7.450Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

7-6: Inter-Pair Skew - D0/D2 Reference: Test ID 7-6

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Data Lane AD0Data Lane BD2Data - Data Inter-Pair Skew(ps)-6.263Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

7-6: Inter-Pair Skew - D1/D2 Reference: Test ID 7-6

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)297.001Data Lane AD1Data Lane BD2Data - Data Inter-Pair Skew(ps)-20.035Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

Test Configuration Details
Device Description
Device ID	Transmitter
Device Name	Device1
Fixture Type	Wilder HDMI2 TPA-P 12 inch
Probe Connection	4 Probes
Probe Head Type	N5380A/B
Lane Connection	1 Data Lane
HDMI Specification	2.0
HDMI Test Type	TMDS Physical Layer Tests
Test Session Details
Infiniium SW Version	06.30.01102
Infiniium Model Number	DSO91304A
Infiniium Serial Number	MY48240287
Application SW Version	2.21
Debug Mode Used	No
Probe (Channel 1)	Model: 1169A Serial: US49412364 Head: N5380A/B Atten: Calibrated (7 NOV 2019 01:44:45), Using Cal Atten (2.0060E+00) Skew: Calibrated (7 NOV 2019 01:51:03), Using Cal Skew
Probe (Channel 2)	Model: 1169A Serial: US54031008 Head: N5380A/B Atten: Calibrated (27 SEP 2019 23:22:31), Using Cal Atten (2.0742E+00) Skew: Calibrated (27 SEP 2019 23:22:51), Using Cal Skew
Probe (Channel 3)	Model: 1169A Serial: US53270632 Head: N5380A/B Atten: Calibrated (7 NOV 2019 01:49:59), Using Cal Atten (2.0456E+00) Skew: Calibrated (7 NOV 2019 01:50:33), Using Cal Skew
Probe (Channel 4)	Model: 1169A Serial: US48470515 Head: N5380A/B Atten: Calibrated (27 SEP 2019 22:57:59), Using Cal Atten (2.1153E+00) Skew: Calibrated (27 SEP 2019 22:58:16), Using Cal Skew
Last Test Date	2019-11-20 21:27:57 UTC -07:00

Test Statistics
Failed	0
Passed	32
Total	32

Margin Thresholds
Warning	< 2 %
Critical	< 0 %

Pass	# Failed	# Trials	Test Name	Worst Actual	Worst Margin	Pass Limits
	0	5	7-9: Clock Jitter	139 mTbit	44.4 %	VALUE <= 250 mTbit
	0	1	7-4: Clock Rise Time	175.175 ps	133.6 %	VALUE >= 75.000 ps
	0	1	7-4: Clock Fall Time	181.407 ps	141.9 %	VALUE >= 75.000 ps
	0	1	7-8: Clock Duty Cycle(Minimum)	50.170	25.4 %	>=40%
	0	1	7-8: Clock Duty Cycle(Maximum)	50.830	15.3 %	<=60%
	0	2	7-2: VL Clock +	2.847 V	17.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL Clock -	2.859 V	13.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Clock	9 mTbit	47.0 %	-150 mTbit <= VALUE <= 150 mTbit
	0	5	7-10: D0 Mask Test	0.000	50.0 %	No Mask Failures
	0	5	7-10: D0 Data Jitter	115 m	61.7 %	<=0.3Tbit
	0	1	7-4: D0 Rise Time	81.951 ps	9.3 %	VALUE >= 75.000 ps
	0	1	7-4: D0 Fall Time	86.966 ps	16.0 %	VALUE >= 75.000 ps
	0	2	7-2: VL D0+	2.794 V	35.3 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D0-	2.799 V	33.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 0	19 mTbit	43.7 %	-150 mTbit <= VALUE <= 150 mTbit
	0	5	7-10: D1 Mask Test	0.000	50.0 %	No Mask Failures
	0	5	7-10: D1 Data Jitter	107 m	64.3 %	<=0.3Tbit
	0	1	7-4: D1 Rise Time	85.216 ps	13.6 %	VALUE >= 75.000 ps
	0	1	7-4: D1 Fall Time	83.257 ps	11.0 %	VALUE >= 75.000 ps
	0	2	7-2: VL D1+	2.878 V	7.3 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D1-	2.881 V	6.3 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 1	17 mTbit	44.3 %	-150 mTbit <= VALUE <= 150 mTbit
	0	5	7-10: D2 Mask Test	0.000	50.0 %	No Mask Failures
	0	5	7-10: D2 Data Jitter	116 m	61.3 %	<=0.3Tbit
	0	1	7-4: D2 Rise Time	88.963 ps	18.6 %	VALUE >= 75.000 ps
	0	1	7-4: D2 Fall Time	88.210 ps	17.6 %	VALUE >= 75.000 ps
	0	2	7-2: VL D2+	2.780 V	40.0 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D2-	2.784 V	38.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 2	-17 mTbit	44.3 %	-150 mTbit <= VALUE <= 150 mTbit
	0	1	7-6: Inter-Pair Skew - D0/D1	2 mTpixel	49.5 %	-200 mTpixel <= VALUE <= 200 mTpixel
	0	1	7-6: Inter-Pair Skew - D0/D2	-2 mTpixel	49.5 %	-200 mTpixel <= VALUE <= 200 mTpixel
	0	1	7-6: Inter-Pair Skew - D1/D2	-6 mTpixel	48.5 %	-200 mTpixel <= VALUE <= 200 mTpixel

Summary of Results

Report Detail