Result Details:

Overall Summary + details of 4 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig	Test Frequency(MHz)	Total Jitter with Zoomed Out Screen	Std Dev(ps)	Tbit(ps)	Clock Jitter(ps)	# Samples	# Edges	Acquisition Bandwidth (GHz)
	Avg	87.08 mTbit	65.30 %
	StdDev	51.74 mTbit	20.71 %
	Range	113.8 mTbit	45.60 %
	Min	27.49 mTbit	43.60 %
	Max	141.3 mTbit	89.20 %
	Sum	348.3 mTbit	261.2 %
	Trial 1 (Worst)	141 mTbit	43.6%	Timing 95	296.704	(See image)	6.032	337.037	47.610	16.000000000 M	0.000	13.000
	Trial 2	117 mTbit	53.2%	Timing 16	148.360	(See image)	13.444	674.035	79.150	16.000000000 M	0.000	13.000
	Trial 3	62 mTbit	75.2%	Timing 4	74.170	(See image)	13.565	1.348253 k	83.760	16.000000000 M	0.000	13.000
	Trial 4	27 mTbit	89.2%	Timing 3	27.000	(See image)	18.908	3.703688 k	101.830	16.000000000 M	0.000	13.000

Trial 1

Trial 1: Total Jitter with Zoomed Out Screen

Trial 1: Clock Jitter

Trial 2

Trial 2: Total Jitter with Zoomed Out Screen

Trial 2: Clock Jitter

Trial 3

Trial 3: Total Jitter with Zoomed Out Screen

Trial 3: Clock Jitter

Trial 4

Trial 4: Total Jitter with Zoomed Out Screen

Trial 4: Clock Jitter

7-4: Clock Rise Time Reference: Test ID 7-4

Test Summary: Pass Test Description: 2 Channels Connection Model: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>= 75.000 psRaw Clock Transition Time164.481 ps

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Upper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)399 mVBase(V)-425 mUpper Threshold(V)234 mLower Threshold(V)-260 m# Edges118.681000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Raw Clock Transition Time

7-4: Clock Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Raw Clock Transition Time

7-8: Clock Duty Cycle(Minimum) Reference: Test ID 7-8

Test Summary: Pass Test Description: 2 Channels Connection Model: Clock duty cycle must be at least 40% and not more than 60%.The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>=40%Clock Duty Cycle Minimum49.780

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704# Edges10.000000 kTdutyMIN(ns)1.678

Trial 1

Trial 1: Clock Duty Cycle Minimum

7-8: Clock Duty Cycle(Maximum) Reference: Test ID 7-8

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704# Edges10.000000 kTdutyMAX(ns)1.700

Trial 1

Trial 1: Clock Duty Cycle Maximum

7-2: VL Clock + Reference: Test ID 7-2

Test Summary: Pass Test Description: The Source shall meet the DC specifications in Table 4-12 for all operating conditions specified in Table 4-11 when driving clock and data signals. For compliance, the DUT should output the lowest supported pixel clock frequency during the test.
Pass Limits:[LowerLimit V to 2.900 V]VL (Worst of 2 Trials)2.849 V # Trials Run: 2Worst Trial: Trial 2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges	DUT supports clock rates > 165MHz
	Avg	2.849 V	17.17 %	3.127 V	2.600 V
	StdDev	565.0 µV	235.7 m%	635.7 µV	0.000 V
	Range	799.0 µV	333.3 m%	899.0 µV	0.000 V
	Min	2.848 V	17.00 %	3.127 V	2.600 V
	Max	2.849 V	17.33 %	3.128 V	2.600 V
	Sum	5.697 V	34.33 %	6.254 V	5.200 V
	Trial 1	2.848 V	17.3%	3.127 V	2.600 V	Timing 3	27.000 MHz	10.762000 k	true
	Trial 2 (Worst)	2.849 V	17.0%	3.128 V	2.600 V	Timing 3	27.000 MHz	10.762000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL Clock - Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges	DUT supports clock rates > 165MHz
	Avg	2.862 V	12.67 %	3.132 V	2.600 V
	StdDev	140.7 µV	238.4 n%	140.7 µV	0.000 V
	Range	199.0 µV	0.000 %	199.0 µV	0.000 V
	Min	2.862 V	12.67 %	3.131 V	2.600 V
	Max	2.862 V	12.67 %	3.132 V	2.600 V
	Sum	5.725 V	25.33 %	6.263 V	5.200 V
	Trial 1 (Worst)	2.862 V	12.7%	3.131 V	2.600 V	Timing 3	27.000 MHz	10.762000 k	true
	Trial 2	2.862 V	12.7%	3.132 V	2.600 V	Timing 3	27.000 MHz	10.762000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Clock Reference: Test ID 7-7

Test Summary: Pass Test Description: Frequency > 165 MHz: Intra-Pair Skew must not exceed 0.15*Tbit. The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:[-150 mTbit to 150 mTbit]Clock Intra-Pair Skew99 mTbit

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)65.390Min skew (ps)-58.590Mean skew (ps)12.328Std Dev (ps)28.121Clk+ threshold (V)2.866Clk- threshold (V)2.858Acquisition Bandwidth (GHz)13.000NumEdges11.051000 kTest Frequency(MHz)296.712Clock Intra-Pair Skew(ps)33.520Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D0 Mask Test Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:No Mask FailuresTotal # failures (Worst of 4 Trials)0.000 # Trials Run: 4Worst Trial: Trial 1

Result Details:

Overall Summary + details of 4 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

200.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

284.370

673.000

296.704

0.000

16.000000000 M

337.037

156 m

52.660

505 m

-463 m

968 m

13.000

Trial 2

0.000

50.0%

Timing 16

589.570

476.000

148.360

44.180

16.000000000 M

674.077

127 m

125 m

85.430

84.375

284 m

-249 m

533 m

13.000

Trial 3

0.000

50.0%

Timing 4

1.249240 k

486.000

74.170

0.000

16.000000000 M

1.348135 k

73 m

72 m

99.010

96.910

290 m

-250 m

540 m

13.000

Trial 4

0.000

50.0%

Timing 3

3.582160 k

486.000

27.000

0.000

16.000000000 M

3.703657 k

33 m

31 m

121.530

115.740

292 m

-253 m

546 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

7-10: D0 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 4 Trials)156 m # Trials Run: 4Worst Trial: Trial 1

Result Details:

Overall Summary + details of 4 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	97.31 m	67.58 %
	StdDev	54.98 m	18.31 %
	Range	123.4 m	41.00 %
	Min	32.81 m	48.00 %
	Max	156.2 m	89.00 %
	Sum	389.2 m	270.3 %
	Trial 1 (Worst)	156 m	48.0%	Timing 95
	Trial 2	127 m	57.7%	Timing 16
	Trial 3	73 m	75.7%	Timing 4
	Trial 4	33 m	89.0%	Timing 3

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

7-4: D0 Rise Time Reference: Test ID 7-4

Test Summary: Pass Test Description: The transition time is defined as the time interval between the normalized 20% and 80% amplitude levels. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:>= 75.000 psTransition Time137.536 ps

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD0Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)505 mVBase(V)-463 mUpper Threshold(V)311 mLower Threshold(V)-269 m#Edge271.018000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D0 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D0+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.868 V	10.67 %	3.138 V	2.600 V
	StdDev	362.0 µV	168.6 n%	8.485 µV	0.000 V
	Range	512.0 µV	0.000 %	12.00 µV	0.000 V
	Min	2.868 V	10.67 %	3.138 V	2.600 V
	Max	2.868 V	10.67 %	3.138 V	2.600 V
	Sum	5.736 V	21.33 %	6.275 V	5.200 V
	Trial 1 (Worst)	2.868 V	10.7%	3.138 V	2.600 V	Timing 3	27.000 MHz	8.273000 k	8.086000 k	true
	Trial 2	2.868 V	10.7%	3.138 V	2.600 V	Timing 3	27.000 MHz	8.181000 k	6.852000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D0- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.868 V	10.83 %	3.133 V	2.600 V
	StdDev	413.7 µV	235.7 m%	413.7 µV	0.000 V
	Range	585.0 µV	333.3 m%	585.0 µV	0.000 V
	Min	2.867 V	10.67 %	3.132 V	2.600 V
	Max	2.868 V	11.00 %	3.133 V	2.600 V
	Sum	5.735 V	21.67 %	6.265 V	5.200 V
	Trial 1 (Worst)	2.868 V	10.7%	3.133 V	2.600 V	Timing 3	27.000 MHz	6.994000 k	8.188000 k	true
	Trial 2	2.867 V	11.0%	3.132 V	2.600 V	Timing 3	27.000 MHz	7.572000 k	7.807000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 0 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)18.560Min skew (ps)-25.100Mean skew (ps)-4.158Std Dev (ps)5.087D+ threshold (V)2.796D- threshold (V)2.767Acquisition Bandwidth (GHz)13.000NumEdges19.966000 kTest Frequency(MHz)296.483Data Intra-Pair Skew(ps)-5.700Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D1 Mask Test Reference: Test ID 7-10

Result Details:

Overall Summary + details of 4 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

200.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

289.120

713.000

296.704

0.000

16.000000000 M

337.038

142 m

47.920

478 m

-493 m

971 m

13.000

Trial 2

0.000

50.0%

Timing 16

586.406

468.000

148.360

41.730

16.000000000 M

674.087

131 m

130 m

88.594

87.539

255 m

-290 m

545 m

13.000

Trial 3

0.000

50.0%

Timing 4

1.249240 k

483.000

74.170

0.000

16.000000000 M

1.348139 k

73 m

72 m

99.010

96.910

260 m

-285 m

545 m

13.000

Trial 4

0.000

50.0%

Timing 3

3.582160 k

489.000

27.000

0.000

16.000000000 M

3.703889 k

34 m

31 m

127.310

115.740

258 m

-292 m

550 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

7-10: D1 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 4 Trials)142 m # Trials Run: 4Worst Trial: Trial 1

Result Details:

Overall Summary + details of 4 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	95.36 m	68.33 %
	StdDev	50.64 m	16.90 %
	Range	107.8 m	36.00 %
	Min	34.37 m	52.67 %
	Max	142.2 m	88.67 %
	Sum	381.4 m	273.3 %
	Trial 1 (Worst)	142 m	52.7%	Timing 95
	Trial 2	131 m	56.3%	Timing 16
	Trial 3	73 m	75.7%	Timing 4
	Trial 4	34 m	88.7%	Timing 3

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

7-4: D1 Rise Time Reference: Test ID 7-4

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD1Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)478 mVBase(V)-493 mUpper Threshold(V)284 mLower Threshold(V)-299 m#Edge266.926000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D1 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D1+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.860 V	13.33 %	3.136 V	2.600 V
	StdDev	770.7 µV	471.4 m%	134.4 µV	0.000 V
	Range	1.090 mV	666.7 m%	190.0 µV	0.000 V
	Min	2.859 V	13.00 %	3.135 V	2.600 V
	Max	2.861 V	13.67 %	3.136 V	2.600 V
	Sum	5.720 V	26.67 %	6.271 V	5.200 V
	Trial 1	2.859 V	13.7%	3.135 V	2.600 V	Timing 3	27.003 MHz	8.074000 k	7.759000 k	true
	Trial 2 (Worst)	2.861 V	13.0%	3.136 V	2.600 V	Timing 3	26.994 MHz	6.839000 k	7.375000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D1- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.860 V	13.33 %	3.130 V	2.600 V
	StdDev	70.71 µV	0.000 %	0.000 V	0.000 V
	Range	100.0 µV	0.000 %	0.000 V	0.000 V
	Min	2.860 V	13.33 %	3.130 V	2.600 V
	Max	2.860 V	13.33 %	3.130 V	2.600 V
	Sum	5.720 V	26.67 %	6.260 V	5.200 V
	Trial 1 (Worst)	2.860 V	13.3%	3.130 V	2.600 V	Timing 3	27.003 MHz	7.891000 k	7.328000 k	true
	Trial 2	2.860 V	13.3%	3.130 V	2.600 V	Timing 3	26.994 MHz	7.482000 k	8.335000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 1 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)9.280Min skew (ps)-26.370Mean skew (ps)-9.389Std Dev (ps)4.987D+ threshold (V)2.790D- threshold (V)2.759Acquisition Bandwidth (GHz)13.000NumEdges18.607000 kTest Frequency(MHz)296.353Data Intra-Pair Skew(ps)-10.970Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-10: D2 Mask Test Reference: Test ID 7-10

Result Details:

Overall Summary + details of 4 worst trials

Pass

Trial

Actual Value

Margin

HDMIAutomationConfig

Eye Width(ps)

Eye Height(mV)

Data Lane A

Test Frequency(MHz)

Mask Moved(ps)

# Acquisitions Point

Tbit(ps)

RightJitterData(Tbit)

LeftJitterData(Tbit)

RightJitterData(ps)

LeftJitterData(ps)

Maximum Margin

Left Margin

Right Margin

Maximum Margin (Vertical)

Upper Margin (Vertical)

Lower Margin (Vertical)

Differential Swing Voltage, VH(V)

Differential Swing Voltage,VL (V)

Differential Swing Voltage(V)

Acquisition Bandwidth (GHz)

Avg

0.000

50.00 %

StdDev

0.000

0.000 %

Range

0.000

0.000 %

Min

0.000

50.00 %

Max

0.000

50.00 %

Sum

0.000

200.0 %

Trial 1 (Worst)

0.000

50.0%

Timing 95

283.320

729.000

296.704

0.000

16.000000000 M

337.039

159 m

53.710

487 m

-515 m

1.002

13.000

Trial 2

0.000

50.0%

Timing 16

583.242

510.000

148.360

22.090

16.000000000 M

674.062

136 m

135 m

91.758

90.703

273 m

-303 m

577 m

13.000

Trial 3

0.000

50.0%

Timing 4

1.261880 k

519.000

74.170

0.000

16.000000000 M

1.348184 k

64 m

63 m

86.370

84.270

276 m

-306 m

581 m

13.000

Trial 4

0.000

50.0%

Timing 3

3.582160 k

529.000

27.000

0.000

16.000000000 M

3.703700 k

33 m

31 m

121.530

115.740

278 m

-307 m

585 m

13.000

Trial 1

Trial 1: Total # failures

Trial 2

Trial 2: Total # failures

Trial 3

Trial 3: Total # failures

Trial 4

Trial 4: Total # failures

7-10: D2 Data Jitter Reference: Test ID 7-10

Test Summary: Pass Test Description: For all channels under all operating conditions specified in Table 4-11 . The Source shall have output levels at TP1, which meet the normalized eye diagram requirements.
Pass Limits:<=0.3TbitTbitCheck (Worst of 4 Trials)159 m # Trials Run: 4Worst Trial: Trial 1

Result Details:

Overall Summary + details of 4 worst trials

Pass	Trial	Actual Value	Margin	HDMIAutomationConfig
	Avg	98.09 m	67.33 %
	StdDev	59.50 m	19.76 %
	Range	126.5 m	42.00 %
	Min	32.81 m	47.00 %
	Max	159.4 m	89.00 %
	Sum	392.4 m	269.3 %
	Trial 1 (Worst)	159 m	47.0%	Timing 95
	Trial 2	136 m	54.7%	Timing 16
	Trial 3	64 m	78.7%	Timing 4
	Trial 4	33 m	89.0%	Timing 3

Trial 1

Trial 1: TbitCheck

Trial 2

Trial 2: TbitCheck

Trial 3

Trial 3: TbitCheck

Trial 4

Trial 4: TbitCheck

7-4: D2 Rise Time Reference: Test ID 7-4

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD2Edge TypeAll edgesUpper Threshold(%)80.000Lower Threshold(%)20.000VTop(V)487 mVBase(V)-515 mUpper Threshold(V)287 mLower Threshold(V)-315 m#Edge269.345000 kAcquisition Bandwidth (GHz)13.000

Trial 1

Trial 1: Transition Time

7-4: D2 Fall Time Reference: Test ID 7-4

Result Details:

Trial 1

Trial 1: Transition Time

7-2: VL D2+ Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.837 V	20.83 %	3.133 V	2.600 V
	StdDev	581.2 µV	235.7 m%	903.7 µV	0.000 V
	Range	822.0 µV	333.3 m%	1.278 mV	0.000 V
	Min	2.837 V	20.67 %	3.133 V	2.600 V
	Max	2.838 V	21.00 %	3.134 V	2.600 V
	Sum	5.675 V	41.67 %	6.267 V	5.200 V
	Trial 1 (Worst)	2.838 V	20.7%	3.133 V	2.600 V	Timing 3	26.985 MHz	6.985000 k	7.469000 k	true
	Trial 2	2.837 V	21.0%	3.134 V	2.600 V	Timing 3	27.017 MHz	7.239000 k	7.160000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-2: VL D2- Reference: Test ID 7-2

Result Details:

Overall Summary + details of 2 worst trials

Pass	Trial	Actual Value	Margin	VH (V)	PassLimit Min (LowerLimit) (V)	HDMIAutomationConfig	Test Frequency	# Edges,VL	# Edges,VH	DUT supports clock rates > 165MHz
	Avg	2.838 V	20.67 %	3.128 V	2.600 V
	StdDev	152.0 µV	0.000 %	859.1 µV	0.000 V
	Range	215.0 µV	0.000 %	1.215 mV	0.000 V
	Min	2.838 V	20.67 %	3.127 V	2.600 V
	Max	2.838 V	20.67 %	3.129 V	2.600 V
	Sum	5.676 V	41.33 %	6.256 V	5.200 V
	Trial 1 (Worst)	2.838 V	20.7%	3.127 V	2.600 V	Timing 3	26.985 MHz	10.078000 k	55.000	true
	Trial 2	2.838 V	20.7%	3.129 V	2.600 V	Timing 3	27.017 MHz	6.984000 k	7.596000 k	true

Trial 1

Trial 1: VL

Trial 2

Trial 2: VL

7-7: Intra-Pair Skew - Data Lane 2 Reference: Test ID 7-7

Result Details:

Result Details
HDMIAutomationConfigTiming 95Max skew (ps)2.740Min skew (ps)-36.070Mean skew (ps)-16.056Std Dev (ps)5.274D+ threshold (V)2.780D- threshold (V)2.747Acquisition Bandwidth (GHz)13.000NumEdges18.647000 kTest Frequency(MHz)296.712Data Intra-Pair Skew(ps)-15.190Intra-Pair Skew Distribution(See image)

Trial 1

Trial 1: Intra-Pair Skew Distribution

7-6: Inter-Pair Skew - D0/D1 Reference: Test ID 7-6

Test Summary: Pass Test Description: Inter-pair skew must not exceed 0.20*Tpixel. The Source shall meet the AC specifications in Table 4-13 across all operating conditions specified in Table 4-11. For compliance, the DUT should output the highest supported pixel clock frequency during the test.
Pass Limits:[-200 mTpixel to 200 mTpixel]Data - Data Inter-Pair Skew2 mTpixel

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD0Data Lane BD1Data - Data Inter-Pair Skew(ps)5.771Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

7-6: Inter-Pair Skew - D0/D2 Reference: Test ID 7-6

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD0Data Lane BD2Data - Data Inter-Pair Skew(ps)19.448Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

7-6: Inter-Pair Skew - D1/D2 Reference: Test ID 7-6

Result Details:

Result Details
HDMIAutomationConfigTiming 95Test Frequency(MHz)296.704Data Lane AD1Data Lane BD2Data - Data Inter-Pair Skew(ps)19.061Triggered Pattern(no value)

Trial 1

Trial 1: Data - Data Inter-Pair Skew

Test Configuration Details
Device Description
Device ID	Transmitter
Device Name	Device1
Fixture Type	Wilder HDMI2 TPA-P 12 inch
Probe Connection	4 Probes
Probe Head Type	N5380A/B
Lane Connection	1 Data Lane
HDMI Specification	2.0
HDMI Test Type	TMDS Physical Layer Tests
Test Session Details
Infiniium SW Version	06.30.01102
Infiniium Model Number	DSO91304A
Infiniium Serial Number	MY48240287
Application SW Version	2.21
Debug Mode Used	No
Probe (Channel 1)	Model: 1169A Serial: US49412364 Head: N5380A/B Atten: Calibrated (12 JUN 2019 16:28:09), Using Cal Atten (2.0150E+00) Skew: Calibrated (12 JUN 2019 16:28:20), Using Cal Skew
Probe (Channel 2)	Model: 1169A Serial: US54031008 Head: N5380A/B Atten: Calibrated (4 JUN 2019 14:32:01), Using Cal Atten (2.0733E+00) Skew: Calibrated (4 JUN 2019 14:32:13), Using Cal Skew
Probe (Channel 3)	Model: 1169A Serial: US53270632 Head: N5380A/B Atten: Calibrated (4 JUN 2019 14:33:01), Using Cal Atten (2.0553E+00) Skew: Calibrated (4 JUN 2019 14:33:12), Using Cal Skew
Probe (Channel 4)	Model: 1169A Serial: US48470515 Head: N5380A/B Atten: Calibrated (4 JUN 2019 14:33:49), Using Cal Atten (2.1284E+00) Skew: Calibrated (4 JUN 2019 14:33:59), Using Cal Skew
Last Test Date	2019-06-13 10:30:38 UTC -06:00

Test Statistics
Failed	0
Passed	32
Total	32

Margin Thresholds
Warning	< 2 %
Critical	< 0 %

Pass	# Failed	# Trials	Test Name	Worst Actual	Worst Margin	Pass Limits
	0	4	7-9: Clock Jitter	141 mTbit	43.6 %	VALUE <= 250 mTbit
	0	1	7-4: Clock Rise Time	164.481 ps	119.3 %	VALUE >= 75.000 ps
	0	1	7-4: Clock Fall Time	164.256 ps	119.0 %	VALUE >= 75.000 ps
	0	1	7-8: Clock Duty Cycle(Minimum)	49.780	24.5 %	>=40%
	0	1	7-8: Clock Duty Cycle(Maximum)	50.430	16.0 %	<=60%
	0	2	7-2: VL Clock +	2.849 V	17.0 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL Clock -	2.862 V	12.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Clock	99 mTbit	17.0 %	-150 mTbit <= VALUE <= 150 mTbit
	0	4	7-10: D0 Mask Test	0.000	50.0 %	No Mask Failures
	0	4	7-10: D0 Data Jitter	156 m	48.0 %	<=0.3Tbit
	0	1	7-4: D0 Rise Time	137.536 ps	83.4 %	VALUE >= 75.000 ps
	0	1	7-4: D0 Fall Time	132.678 ps	76.9 %	VALUE >= 75.000 ps
	0	2	7-2: VL D0+	2.868 V	10.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D0-	2.868 V	10.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 0	-17 mTbit	44.3 %	-150 mTbit <= VALUE <= 150 mTbit
	0	4	7-10: D1 Mask Test	0.000	50.0 %	No Mask Failures
	0	4	7-10: D1 Data Jitter	142 m	52.7 %	<=0.3Tbit
	0	1	7-4: D1 Rise Time	145.607 ps	94.1 %	VALUE >= 75.000 ps
	0	1	7-4: D1 Fall Time	132.764 ps	77.0 %	VALUE >= 75.000 ps
	0	2	7-2: VL D1+	2.861 V	13.0 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D1-	2.860 V	13.3 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 1	-33 mTbit	39.0 %	-150 mTbit <= VALUE <= 150 mTbit
	0	4	7-10: D2 Mask Test	0.000	50.0 %	No Mask Failures
	0	4	7-10: D2 Data Jitter	159 m	47.0 %	<=0.3Tbit
	0	1	7-4: D2 Rise Time	142.315 ps	89.8 %	VALUE >= 75.000 ps
	0	1	7-4: D2 Fall Time	135.719 ps	81.0 %	VALUE >= 75.000 ps
	0	2	7-2: VL D2+	2.838 V	20.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	2	7-2: VL D2-	2.838 V	20.7 %	LowerLimit V <= VALUE <= 2.900 V
	0	1	7-7: Intra-Pair Skew - Data Lane 2	-45 mTbit	35.0 %	-150 mTbit <= VALUE <= 150 mTbit
	0	1	7-6: Inter-Pair Skew - D0/D1	2 mTpixel	49.5 %	-200 mTpixel <= VALUE <= 200 mTpixel
	0	1	7-6: Inter-Pair Skew - D0/D2	6 mTpixel	48.5 %	-200 mTpixel <= VALUE <= 200 mTpixel
	0	1	7-6: Inter-Pair Skew - D1/D2	6 mTpixel	48.5 %	-200 mTpixel <= VALUE <= 200 mTpixel

Summary of Results

Report Detail